Energy-efficient, On-demand Reprogramming of Large-scale Sensor Networks

As sensor networks operate over long periods of deployment in difficult to reach places, their requirements may change or new code may need to be uploaded to them. The current state of the art protocols (Deluge and MNP) for network reprogramming perform the code dissemination in a multi-hop manner using a three way handshake whereby meta-data is exchanged prior to code exchange to suppress redundant transmissions. The code image is also pipelined through the network at the granularity of pages. In this paper we propose a protocol called Freshet for optimizing the energy for code upload and speeding up the dissemination if multiple sources of code are available. The energy optimization is achieved by equipping each node with limited non-local topology information, which it uses to determine the time when it can go to sleep since code is not being distributed in its vicinity. The protocol to handle multiple sources provides a loose coupling of nodes to a source and disseminates code in waves each originating at a source, with mechanism to handle collisions when the waves meet. The protocol’s performance with respect to reliability, delay, and energy consumed, is demonstrated through analysis, simulation, and implementation on the Berkeley mote platform

Test Planning for Modular Testing of Hierarchical SOCs

Abstract—Multilevel test access mechanism (TAM) optimization is necessary for modular testing of hierarchical systems-on-chip (SOCs) that contain older-generation SOCs as embedded megacores. We consider the case where these older-generation SOCs are used as hard cores in new SOC designs, and they are delivered to the system integrator as optimized and technology-mapped layouts. We present three hierarchical test planning and TAM optimization flows that exploit recent advances in TAM design for flattened SOC hierarchies. These techniques are based on the reuse of existing TAM architectures within megacores and the optimization of the top-level TAM under the constraints imposed by “TAM-ed ” megacores that are delivered either with or without a wrapper. We present a new megacore wrapper-design technique for the latter case. Unlike prior methods that assume flat test hierarchies, the proposed methods are directly applicable to real-world design-transfer models involving hard megacores between the core vendor and the system integrator for hierarchical SOCs. Experimental results are presented for four ITC’02 SOC test benchmarks that contain megacores. Index Terms—Design transfer and hand-off model, hard cores, megacores, test access mechanism (TAM), TAM optimization, testing time, test wrappers. I

Test Cost Reduction for SOCs Using Virtual TAMs and Lagrange Multipliers

Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically run at lower frequencies (10-50 MHz). The use of high-speed ATE channels to drive slower scan chains leads to an underutilization of resources, thereby resulting in an increase in testing time. We present a new technique to reduce the testing time and test cost by matching highspeed ATE channels to slower scan chains using the concept of virtual test access mechanisms (TAMs). We also present a new TAM optimization framework based on Lagrange multipliers. Experimental results are presented for three industrial circuits from the ITC'02 SOC test benchmarks